1. Field
Example embodiments relate to methods of manufacturing semiconductor devices. More particularly, example embodiments relate to methods of manufacturing semiconductor devices showing a high performance and including ultra small size transistors.
2. Description of the Related Art
Miniaturization of patterns may be an essential factor for forming highly integrated semiconductor devices. Nowadays, ultra small size semiconductor devices may have a high operating speed and having a gate length of, e.g., about 40 nm or less, have been manufactured.
For the ultra small size semiconductor devices including transistors having the high operating speed, an area of a channel region provided under a gate electrode may be comparatively small when compared to that of the conventional semiconductor devices. Mobility of electrons or holes traveling through the channel region may be largely affected by, e.g., an applied stress to the channel region. Accordingly, various studies on optimizing a strength of the stress applied to the channel region and on improving the operating speed of the semiconductor devices have been widely conducted.
A hole mobility may be smaller than an electron mobility for semiconductor devices including a silicon substrate as a channel. Therefore, an increase of an operating speed of a p-channel MOS transistor using the holes as carriers may be important when designing an integrated semiconductor circuit device.
For the p-channel MOS transistor, the hole mobility may increase by applying a uniaxial compressive stress to the channel region. To explain an applying means of the compressive stress to the channel region, an exemplary schematic constitution of a cross-sectional view a p-MOS transistor is illustrated in FIG. 1.
Referring to FIG. 1, on a silicon substrate 1, a gate insulating layer 2 and a gate electrode 3 corresponding to a channel region may be formed. In the substrate 1 at both side portions of the gate electrode 2, p-type diffusion regions 1a and 1b for defining the channel region may be formed. On side walls of the gate electrode 3, sidewall spacers 3A and 3B may be formed.
The diffusion regions 1a and 1b may respectively function as an extension region of a source and a drain of the MOS transistor. The flowing of the holes moving through the channel region under the gate electrode 3 may be controlled by a gate voltage applied to the gate electrode 3.
Referring to FIG. 1 again, SiGe mixed crystal layers 1A and 1B may be formed in the silicon substrate 1 at both exterior sides of the sidewall spacers 3A and 3B. In the SiGe mixed crystal layers 1A and 1B, p-type source and drain regions, respectively contacting the diffusion regions 1a and 1b may be formed.
For the MOS transistor having the constitution illustrated in FIG. 1, since the SiGe mixed crystal layers 1A and 1B may have a larger lattice constant than that of the silicon substrate 1, a compressive stress may be formed as designated by an arrow ‘a’ in the SiGe mixed crystal layers 1A and 1B. Thus, a bending stress approximately vertical to a surface portion of the silicon substrate 1 and designated by an arrow ‘b’ may be generated in the SiGe mixed crystal layers 1A and 1B.
Since the SiGe mixed crystal layers 1A and 1B may be formed through an epitaxial growing process from the silicon substrate 1, a bending stress may be generated in a vertical direction as designated by an arrow ‘c’ in the channel region of the silicon substrate in accordance with the stress of the SiGe mixed crystal layers 1A and 1B as designated by the arrow ‘b’. In addition, a uniaxial compressive stress may be generated as designated by an arrow ‘d’ similar to the above-described bending stress in the channel region.
For the MOS transistor in FIG. 1, a symmetric property of a silicon crystal constituting the channel region may be locally deformed through the application of the uniaxial compressive stress to the channel region. In accordance with a change of the symmetric property, a valence band of heavy holes and a valence band of light holes may be untied and the hole mobility in the channel region may increase and so an operating speed of the transistor may increase. The increase of the hole mobility due to the local separation of the stress in the channel region and resulting improvement of the operating speed of the transistor may be particularly shown in ultra small size semiconductor devices having a gate length of about 50 nm or less.
In Korean Patent No. 10-0657395 B1 published on Dec. 7, 2006, a detailed description on background of the above-described technique is disclosed on page 5, lines 1-22 referring to FIG. 1.
FIG. 2 is a cross-sectional view of a p-MOS transistor having another structure.
In FIG. 2, a MOS transistor including a capping layer 40 having a silicon facet (Si facet) to prevent consumption or deterioration of a SiGe mixed crystal layer 35 is illustrated.
Referring to FIG. 2, in order to form the capping layer 40 including the silicon facet on the SiGe mixed crystal layer 35, a large amount of hydrogen chloride (HCl) may be introduced while performing an epitaxial growing process of silicon to form the capping layer 40 including an inclined sidewall. However, when the large amount of hydrogen chloride is supplied, a pit may be probably generated at the capping layer 40 including the silicon facet. In addition, a growing rate of silicon while performing the epitaxial growing process may be largely decreased due to the introduction of hydrogen chloride.
In this case, a processing temperature may be increased to increase the growing rate of the layer sufficiently. When the processing temperature is increased, defects may be generated due to a thermal budget.